The present invention relates to splitting the input power of an input signal and accordingly generating a plurality of output signals, and more particularly, to an on-chip transformer power splitter implemented in a system that has high transformer coupling efficiency and high power splitting efficiency.
Power combining technique is commonly employed in a power amplifier of a wireless communication system to provide signals to be transmitted (e.g., RF signals) with sufficient signal power. One possible power combining implementation is to use a transformer power combiner. Please refer to FIG. 1, which is a schematic diagram illustrating a conventional power amplifier system. The power amplifier system 100 includes a transformer power combiner 102 and a plurality of power amplifiers 104_1, 104_2, . . . , 104_N. Each of the power amplifiers 104_1, 104_2, . . . , 104_N can be modeled by an RF current source i1, i2, . . . , iN connected to an impedance rS in parallel. In addition, parasitic impedance r also exists in the transformer power combiner 102.
Provided that the turn ratio is 1:1, the output voltage across the load impedance rL is equal to a sum of the input voltage levels V1, V2, . . . , VN respectively presented at the input ports of the transformer power combiner 102. The input impedance Zin seen by a specific power amplifier at a corresponding input port can be expressed as equation (1) below:
                              Z                      in            ,            i                          =                                                            (                                                      2                    ⁢                                                                                  ⁢                    r                                    +                                                            r                      L                                        N                                                  )                            ⁢                              i                i                                      +                                          r                S                            ⁡                              (                                                      i                    i                                    -                                                            1                      N                                        ⁢                                                                  ∑                                                  i                          =                          1                                                N                                            ⁢                                              i                        i                                                                                            )                                                                        1              N                        ⁢                                          ∑                                  i                  =                  1                                N                            ⁢                              i                i                                                                        (        1        )            
In an ideal case where i1=i2= . . . =ij= . . . =iN (i.e., the current i flowing through each primary winding is equal to the current i flowing through the secondary windings), the input impedance seen by each power amplifier is the same, namely
      Z    in    =            2      ⁢      r        +                            r          L                N            .      In other words, in the ideal case, the input signals fed into the input ports of the transformer power combiner 102 are constructively synchronous with one another in phase and amplitude, whereby the optimum power combining efficiency could be achieved for delivering maximum power at the output port of the transformer power combiner 102. However, for the on-chip transformer power combiner employed in the power amplifier system manufactured utilizing a silicon technology such as a CMOS technology, the capacitive coupling among the primary and secondary windings adversely exists. As a result, the input signals fed into the input ports of the transformer power combiner 102 do not keep synchronous with one another because the input impedance seen by each power amplifier is not equal to the same value due to the undesired capacitive coupling.
For example, in a case where
      i    j    =      -                  ∑                              i            =            1                                i            ≠            j                          N            ⁢              i        i            caused by the undesired capacitive coupling, the corresponding input impedance Zin,j is infinitely large (i.e., Zin,j=∞), meaning that the input port is an open circuit; in another case where
      (                  i        j            +                        ∑                                    i              =              1                                      i              ≠              j                                N                ⁢                  i          i                      )    <  0caused by the undesired capacitive coupling, the corresponding input impedance Zin,j is a negative value (i.e., Zin,j<0), meaning that the system would become unstable.
Briefly summarized, the on-chip transformer power combiner under deep-scaled technology is sure to suffer greatly from the capacitive coupling. For example, the load impedance seen by the power amplifier may not match to an optimum impedance value desired by the power amplifier. As a result, the power combining efficiency is degraded and the actual output power fails to reach the maximum value as desired. Furthermore, it is possible that the load impedance seen by the power amplifier becomes negative. As a result, power delivered from the power amplifier would be returned from the output port of the transformer power combiner, resulting in system unstability. In addition, as illustrated by the aforementioned equation (1) showing that the input impedance at each input port is highly dependent upon characteristics of other input ports, the nonlinearity of the output power generated from the transformer power combiner occurs due to the varying amplitude/phase of the input signal fed into each input port of the transformer power combiner.
There are many conventional ways to implement the transformer using metal conductors routed in an integrated circuit. For example, an on-chip transformer can be implemented using a one-side coplanar design, a two-side coplanar design, a broadside design, or a hybrid design. In general, the on-chip transformer with better coupling efficiency and less coupling loss causes more capacitive coupling among the primary and secondary windings, thus resulting in poor power combining efficiency and/or system instability as mentioned above. That is, using highly resistive and highly capacitive metal layers in deep scaled technology to build circuit components induces large coupling capacitance for the low-loss transformer design, leading to imbalanced and inefficient power combining result, especially for high-frequency application (e.g., the mmWave application). In a worst case, the overall system is unstable.
Therefore, these is a trade-off between two design parameters, transformer efficiency and power combining efficiency, for the conventional on-chip transformer power combiner design. A solution which can unbind these two design parameters is highly desired for power amplifier systems, especially for those power amplifier systems operated under high frequency such as the frequency about 60 GHz or above in mmWave application.
Regarding the power splitting technique, it is also commonly employed in a wireless communication system to accept an input signal (e.g., an RF signal) and then deliver multiple output signals with specific phase and amplitude characteristics. One possible power splitting implementation is to use a transformer power splitter. In an ideal case, the output signals appearing at the output ports of the transformer power splitter are synchronous with one another in phase and amplitude, whereby the optimum power splitting efficiency could be achieved due to evenly splitting the input power at the input port of the transformer power splitter. However, for the on-chip transformer power splitter employed in the power splitting system manufactured utilizing a silicon technology such as a CMOS technology, the capacitive coupling among the primary and secondary windings adversely exists. As a result, the power splitting efficiency may be degraded. As mentioned above, these is a trade-off between two design parameters, transformer efficiency and power combining efficiency, for the conventional on-chip transformer power combining design. Similarly, these is also a trade-off between two design parameters, transformer efficiency and power splitting efficiency, for the conventional on-chip transformer power splitter design. Therefore, a solution which can unbind these two design parameters is also highly desired for wireless communication systems, especially for those wireless communication systems operated under high frequency such as the frequency about 60 GHz or above in mmWave application.